1. Field of the Invention
The present invention relates to a semiconductor memory, and in particular, relates to a semiconductor memory in which a memory cell array is divided into a plurality of memory banks that can be accessed independently.
2. Description of the Related Art
In semiconductor memory devices in recent years, the miniaturization of memory cells and peripheral circuits that has accompanied the great increase in memory capacity has brought with it an increase in the incidence of defective parts that are unintentionally incorporated. Semiconductor memory device are therefore provided with both normal memory cells, which are memory cells for normal use, and redundant memory cells, which substitute when a defect occurs in a normal memory cell; and the defect remedy technology for replacing normal memory cells in which defects have been detected (hereinbelow referred to as “defective memory cells”) with redundant memory cells to improve productivity yield has become a crucial technology.
In order to replace a defective memory cell with a redundant memory cell, the address of the defective memory cell (hereinbelow referred to as “failed addresses”) must be stored. Nonvolatile memory elements for storing fail addresses include fuses in which a conductor is fused and insulated by a laser or electric current, and antifuses in which an overvoltage is applied to an insulator to break down the insulator in order to cause conduction.
In fuses that are typically used as in semiconductor memory devices of the prior art, a laser light is used when testing the memory chip to fuse conductors and thus store fail addresses, and as memory elements, these fuses have relatively stable characteristics. However, the method in which a laser is used to melt a fuse and store fail addresses suffers from the problem that, once a memory chip has been sealed within a package (assembled), defects that are detected can no longer be remedied, and this method is therefore unable to adequately improve productivity yield. In recent years, however, antifuses are coming into use that are capable of remedying defective memory cells even after assembly.
The antifuse can write address information of the defective cells with a relatively small current, and the antifuse can not only relieve defects after the assembly has been sealed, but can also carry out testing a device with the function of short-circuiting the antifuse element at comparatively low cost.
Japanese Patent Laid-Open No. 2004-55100 discloses a technique in which, in a memory module provided with a plurality of volatile memories and a nonvolatile memory, the fail address of volatile memories that are judged to be defects in memory module testing and the information that is used to distinguish the volatile memories are stored in nonvolatile memory, the information is transferred from nonvolatile memory to the volatile memories upon start-up of the system, and access is made to a corresponding redundant memory cell when access is made to the fail address in the volatile memories, thereby relieving the volatile memories that are already mounted on the memory module.
For a semiconductor memory in which a memory cell array is divided into a plurality of memory banks that can be accessed independently, it is necessary to provide a plurality of redundant memory cells that are to be used in the respective memory cells. In particular, productivity yields of semiconductor memories can be improved when the plurality of redundant memory cells can be shared by each memory cell, and the control circuit for redundant memory cells can be further simplified when the plurality of redundant memory cells are arranged together. However, according to the configuration in which a plurality of redundant memory cells is arranged together, an exclusive area for these cells must be ensured. Also, usually, since redundant memory cells are arranged away from memory banks, it is necessary to use a large amount of wiring becomes long which causes an increase in the layout area. Further, there is a possibility that access time to the memory cells becomes longer.
In recent information processing devices and the like, because of the increased speed of processing devices, such as CPUs, the access time in semiconductor memory causes a bottomneck for the processing speed of the information processing device. For that reason, further demands are made on the increase in memory capacity and on shortening of the access time.